Dissipation of a charge buildup on a wafer portion

Details Dissipation of a charge buildup on a wafer portion Dissipation of a charge buildup on a wafer portion

2006-05-02

2006-05-02

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S751000

Reexamination Certificate

active

07038293

ABSTRACT:
An apparatus in one example comprises a wafer portion that comprises a conduction layer. Upon exposure of the conduction layer during a etch of the wafer portion, the conduction layer serves to dissipate a portion of a charge buildup on the wafer portion during an etch of the wafer portion.

REFERENCES:
patent: 5129981 (1992-07-01), Wang et al.
patent: 5865938 (1999-02-01), Peeters et al.
patent: 6333246 (2001-12-01), Narita et al.
patent: 6812145 (2004-11-01), Ma
patent: 2002/0104821 (2002-08-01), Bazylenko et al.

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