Entering and exiting power managed states without disrupting...

Computer graphics processing and selective visual display system – Computer graphic processing system – Interface

Reexamination Certificate

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Details

C713S320000, C713S323000, C713S324000, C713S330000, C713S340000, C710S305000, C345S531000, C345S532000, C345S533000

Reexamination Certificate

active

07027057

ABSTRACT:
An interface between an accelerated graphics port graphics controller (AGP-GC) and a core controller to prevent entry into a low power state from interfering with transfers to or from the AGP-GC that have been requested but not completed. The core controller can communicate to the AGP-GC an intent to enter a low power state, while the AGP-GC can communicate to the core controller the busy status of the AGP-GC. When the AGP-GC receives notice of an intent to enter a low power state, it can stop issuing requests to the core controller. When the core controller detects that the AGP-GC is busy, the core controller can postpone entry into the low power state until the AGP-GC completes any requests that are in progress. In an alternate use of the interface, if the AGP-GC wishes to make a request during a low power state, it can signal the core controller of this need by indicating a busy status, which can trigger the core controller to initiate an exit from the low power state.

REFERENCES:
patent: 5471625 (1995-11-01), Mussemann et al.
patent: 5659715 (1997-08-01), Wu et al.
patent: 6021506 (2000-02-01), Cho et al.
patent: 6052133 (2000-04-01), Kang
patent: 6292201 (2001-09-01), Chen et al.
patent: 6434688 (2002-08-01), Rhoden et al.
patent: 6738068 (2004-05-01), Cohen et al.

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