Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2006-10-17
2006-10-17
Sarkar, Asok K. (Department: 2891)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S393000, C438S622000, C257SE21647, C257SE21664
Reexamination Certificate
active
07122441
ABSTRACT:
In one embodiment, a plurality of bottom electrodes spaced apart from each other are formed on a lower insulating layer. A high-k dielectric layer and an upper conductive layer are sequentially and conformally formed overlying the bottom electrodes. The high-k dielectric layer and the upper conductive layer cover the bottom electrodes and the lower insulating layer between the bottom electrodes. A hard mask layer is selectively formed on the upper conductive layer to have an overhang over each of the bottom electrodes. Then the upper conductive layer is anisotropically etched using the hard mask layer as an etch mask, thereby forming upper electrodes spaced from each other. Therefore, a photolithography process of forming upper electrodes can be omitted, and damage to the upper electrodes due to etch can be prevented.
REFERENCES:
patent: 6211035 (2001-04-01), Moise et al.
patent: 2002/0014646 (2002-02-01), Tsu et al.
patent: 2004/0178451 (2004-09-01), Yagishita et al.
patent: 2002-094014 (2002-03-01), None
patent: 2001-0005096 (2001-01-01), None
patent: 2002-0018865 (2002-03-01), None
English language abstract of Korean Publication No. 2001-0005096.
English language abstract of Korean Publication No. 2002-0018865.
English language abstract of Japanese Publication No. 2002-094014.
Kim Hyun-Ho
Park Jung-Hoon
Sarkar Asok K.
Yevsikov Victor V.
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