Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2006-08-01
2006-08-01
Elms, Richard (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S185200, C365S203000, C365S210130
Reexamination Certificate
active
07085148
ABSTRACT:
A semiconductor memory device having a semiconductor substrate includes a plurality of reference cells4and a plurality of bit lines10. The reference cells4are formed in a region near the centerline of a predetermined region of the semiconductor substrate which is perpendicular to the bit lines10. The bit lines10form pairs each composed of two adjacent bit lines. Two bit lines10in each pair have a first parallel state and a second parallel state in which positions of the two bit lines are reversed from the first parallel state. Each pair of bit lines10has at least one cross section11where one of the pair of bit lines10crosses the other, to switch between the first parallel state and the second parallel state. The cross section11is provided in the predetermined region of the semiconductor substrate such that the length of a bit line10in the first parallel state is equal to the length of the bit line10in the second parallel state. The semiconductor memory device is reduced in size.
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Iwanari Shunichi
Murakuki Yasuo
Sakagami Masahiko
Elms Richard
Luu Pho M.
Matsushita Electric - Industrial Co., Ltd.
McDermott Will & Emery LLP
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