Method for improving latchup immunity in a dual-polysilicon gate

Details Method for improving latchup immunity in a dual-polysilicon gate Method for improving latchup immunity in a dual-polysilicon gate

1993-08-13

1995-05-30

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437 63, 437 65, 437 67, 437 78, H01L 2710, H01L 27302

Patent

active

054200610

ABSTRACT:
The invention is a method for creating a portion of an integrated circuit on a semiconductor wafer. The invention comprises doping a substrate to form a doped well region having an opposite conductivity type than the substrate. Separate photomasking steps are used to define N-channel and P-channel metal oxide semiconductor (MOS) transistor gates. A trench is formed near the well without using additional masking steps. The trench improves the latch up immunity of the device. The invention is also the apparatus created by the method and comprises a trench positioned in the substrate to interrupt the conduction of minority carriers between two regions of the substrate. Thus, the invention improves latch up immunity without additional process complexity.

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