Clock divider of delay locked loop

Details Clock divider of delay locked loop Clock divider of delay locked loop

2006-07-25

2006-07-25

Wells, Kenneth B. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

C327S115000

Reexamination Certificate

active

07082179

ABSTRACT:
A divider of a DLL(delay locked loop) measures tAC for various periods due to variation of process, temperature and a supply voltage and provides a divided clock having an optimum tAC. The clock divider includes a clock dividing unit, a test mode clock providing unit and a normal mode clock providing unit. The clock dividing unit receives a source clock of the DLL to generate a plurality of divided clocks, each having a period different from each other. The test mode clock providing unit selectively outputs the plurality of the divided clocks in a test mode in response to a test mode signal and a test mode period selecting signal. And, the normal mode clock providing unit outputs selected one of the plurality of the divided clocks in a normal mode in response to the test mode signal.

REFERENCES:
patent: 6651181 (2003-11-01), Lacey
patent: 6815985 (2004-11-01), Jeon
patent: 6877123 (2005-04-01), Johnston et al.
patent: 1998-68005 (1998-10-01), None

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