Semiconductor package for three-dimensional mounting,...

Details Semiconductor package for three-dimensional mounting,... Semiconductor package for three-dimensional mounting,...

2006-04-18

2006-04-18

Zarneke, David A. (Department: 2891)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Insulative housing or support

Reexamination Certificate

active

07029953

ABSTRACT:
A semiconductor package for three-dimensional mounting is provided. The package includes a wiring substrate having a first surface on which a first wiring pattern is formed and a second surface on which a second wiring pattern is formed, the first wiring pattern and second wiring pattern being electrically connected to each other; a semiconductor chip placed on the first surface of the wiring substrate and electrically connected to the first wiring pattern; a sealing resin layer sealing the semiconductor chip and the first wiring pattern; a thickness direction wire passing through the sealing resin layer in a thickness direction and having one end electrically connected to the first wiring pattern and the other end exposed at the surface of the sealing resin layer; and a lower surface connecting electrode formed on the second surface of the wiring substrate and electrically connected to the second wiring pattern.

REFERENCES:
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patent: 6348728 (2002-02-01), Aiba et al.
patent: 6429528 (2002-08-01), King et al.
patent: 6451624 (2002-09-01), Farnworth et al.
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patent: 09-069587 (1997-11-01), None
patent: 11-186492 (1999-07-01), None
patent: 2000-294720 (2002-10-01), None
Lau, Flip Chip Technologies, 1996, McGraw-Hill, pp. 27-31, Figures 1.27, 1.29b.

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