System and method for input/output induced latch up detection

Details System and method for input/output induced latch up detection System and method for input/output induced latch up detection

2006-01-10

2006-01-10

Tang, Minh N. (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S762010

Reexamination Certificate

active

06985002

ABSTRACT:
The present invention is directed to a system and method of testing an integrated circuit (IC) device for potential latch-up. The system has a power supply configured to supply a maximum voltage to the integrated circuit device. The system uses a current measuring device for measuring current between the power supply and the circuit device. The system includes an overvoltage source that is operative to apply an overvoltage pulse to one input pin that is designated a test pin while the maximum supply voltage is applied to each other input pin of the integrated circuit device. The current measuring device detects whether a latch up condition exists by detecting an increase in current between the power supply and the device based application of the overvoltage pulse.

REFERENCES:
patent: 5825600 (1998-10-01), Watt
patent: 6469538 (2002-10-01), Gupta
patent: 6636067 (2003-10-01), Salcedo-Suner
Jorge Salcedo-Suner, “A New Induced Latchup Phenomenon Generated By Overvoltage Stress In Voltage Tolerant ESD Protection Circuits”, Texas Instruments, Inc, (date unknown).

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