Method and apparatus for use in booth-encoded multiplication

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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Reexamination Certificate

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07024445

ABSTRACT:
A new partial product bit generator is used to generate a partial product bit PPji. In some embodiments, the partial product bit generator generates the partial product bit PPjifrom intermediate signals that are able to be generated concurrently, for example in two levels of combinatorial logic. The partial product bit PPjiis then able to be generated from the intermediate signal, for example in only one level of combinatorial logic. In such embodiments, a long series of combinatorial logic operations is not required.

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Goto et al., “A 4.1-ns Compact 54×54-b Multiplier Utilizing Sign-Select Booth Encoders”, IEEE Journal of Solid-State Circuits, vol. 32, No. 11 Nov. 1997; pp. 1676-1681.
Ohkubo et al., “A 4.4 ns CMOS 54×54-b Multiplier Using Pass-Transistor Multiplexer”, IEEE Journal of Solid-State Circuits, vol. 30, No. 3, Mar. 1995, pp. 251-257.
Yeh et al., “High-Speed Booth Encoded Parallel Multiplier Design” IEEE Transactions on Computers, vol. 49, No. 7, Jul. 2000, pp. 692-710.

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