Method and apparatus for reducing cache thrashing

Details Method and apparatus for reducing cache thrashing Method and apparatus for reducing cache thrashing

2006-09-12

2006-09-12

Dam, Tuan (Department: 2192)

Data processing: software development, installation, and managem

Software program development tool

Translation of code

C717S160000

Reexamination Certificate

active

07107583

ABSTRACT:
A method for compiling a program to reduce the possibility of cache thrashing is provided. The method comprises identifying a loop in a program, identifying each vector memory reference in the loop, and determining dependencies between the vector memory references in the loop. Determining the dependencies includes determining unidirectional and circular dependencies. Thereafter, the vector memory references are distributed into a plurality of detail loops, wherein the vector memory references that have circular dependencies therebetween are included in a common detail loop, and the detail loops are ordered according to the unidirectional dependencies between the memory references.

REFERENCES:
patent: 5704053 (1997-12-01), Santhanam
patent: 5797013 (1998-08-01), Mahadevan et al.
patent: 5862385 (1999-01-01), Iitsuka
patent: 5950007 (1999-09-01), Nishiyama et al.
patent: 6539541 (2003-03-01), Geva
Carr, et al., “Compiler Optimizations for Improving Data Locality”, 1994, ACM, p. 252-262.

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