Method and system for providing hierarchical self-checking...

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation

Reexamination Certificate

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Details

C703S013000, C703S015000, C703S022000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

07072816

ABSTRACT:
A method and system for providing simulation of an integrated circuit during development of the integrated circuit is disclosed. The integrated circuit has an island that includes an interface. The method and system include a snooper, a checker and a generator. The snooper is coupled with an interface and is for obtaining an output provided by the island during simulation. The checker is coupled with an interface and is for checking the output to determine whether the output is a desired output. The generator is coupled with an interface and is for providing an input to the interface during simulation. The generator is coupled with a test case that directs the generator.

REFERENCES:
patent: 4817093 (1989-03-01), Jacobs et al.
patent: 4914612 (1990-04-01), Beece et al.
patent: 5187712 (1993-02-01), Malleo-Roach et al.
patent: 5457697 (1995-10-01), Malleo-Roach et al.
patent: 5510999 (1996-04-01), Lee et al.
patent: 5517637 (1996-05-01), Bruce, Jr. et al.
patent: 5572437 (1996-11-01), Rostoker et al.
patent: 5633812 (1997-05-01), Allen et al.
patent: 5675545 (1997-10-01), Madhavan et al.
patent: 5958011 (1999-09-01), Arimilli et al.
patent: 6006024 (1999-12-01), Guruswamy et al.
patent: 6083269 (2000-07-01), Graef et al.
patent: 6157972 (2000-12-01), Newman et al.
patent: 6161189 (2000-12-01), Arimilli et al.
patent: 6175946 (2001-01-01), Ly et al.
patent: 6182258 (2001-01-01), Hollander
patent: 6292931 (2001-09-01), Dupenloup
patent: 6360191 (2002-03-01), Koza et al.
patent: 6378123 (2002-04-01), Dupenloup
patent: 6563159 (2003-05-01), Kunikiyo et al.
patent: 06348781 (1994-12-01), None
“A Model for SIMOX Buried-Oxide High-Field Conductiion”, Krska et al, IEEE Transactions on Electron Devices, vol. 43, No. 11, Nov. 1996.
“Versatile Testcase Driver For System Simulation,”IBM Technical Disclosure Bulletin, vol. 32, No. 8A, Jan. 1990.
“Electronic Card Fault Simulator to Building Block Tester Data Path,”IBM Technical Disclosure Bulletin, vol. 37, No. 08, Aug. 1994.

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