Method for stressing oxide in MOS devices during fabrication usi

Details Method for stressing oxide in MOS devices during fabrication usi Method for stressing oxide in MOS devices during fabrication usi

1995-11-08

1998-08-25

Bowers, Jr., Charles L.

Semiconductor device manufacturing: process

With measuring or testing

438 12, 438 17, 324765, H01L 2100

Patent

active

057982813

ABSTRACT:
A method and apparatus are disclosed for stressing the oxide layer (36) of an MOS integrated circuit during the fabrication process. One aspect of the invention is a method for fabricating an MOS integrated circuit. In accordance with this method, an oxide layer (36) is formed on a semiconductor substrate (34), and a gate layer (38) is formed on top of the oxide layer (36). During fabrication of the MOS integrated circuit, a potential is applied between the gate layer (38) and the semiconductor substrate (34) in order to stress the oxide layer (36). Other aspects of the invention include applying both a forward and reverse potential to stress the oxide layer (36). Also, the oxide stress can be applied at an elevated temperature. Elevated temperature aids in stressing the oxide layer (36).

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Joseph King, Wilson Chan and Chenming Hu, "Efficient Gate Oxide Defect Screen for VLSI Reliability", paper presented in Technical Digest --International Electron Devices Meeting, San Francisco, California. Dec. 1994.

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