Non-volatile semiconductor memory device

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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Details

C365S185120, C365S185220

Reexamination Certificate

active

07038946

ABSTRACT:
A non-volatile semiconductor memory device includes a memory cell array with electrically rewritable non-volatile memory cells laid out therein, an address selector circuit for performing memory cell selection of the memory cell array, a data read/write circuit arranged to perform data read of the memory cell array and data write to the memory cell array, and a control circuit for executing a series of copy write operations in such a manner that a data output operation of from the data read/write circuit to outside of a chip and a data write operation of from the data read/write circuit to the memory cell array are overlapped each other, the copy write operation including reading data at a certain address of the memory cell array into the data read/write circuit, outputting read data held in the read/write circuit to outside of the chip and writing write data into another address of the memory cell array, the write data being a modified version of the read data held in the data read/write circuit as externally created outside the chip.

REFERENCES:
patent: 5465235 (1995-11-01), Miyamoto
patent: 6195286 (2001-02-01), Pascucci
patent: 6411548 (2002-06-01), Sakui et al.
patent: 6661706 (2003-12-01), Imamiya et al.
patent: 6671204 (2003-12-01), Im
patent: 6687158 (2004-02-01), Yano
patent: 6731540 (2004-05-01), Lee et al.
patent: 2002/0126531 (2002-09-01), Hosono et al.
patent: 07-122092 (1995-05-01), None
patent: 11-175391 (1999-07-01), None

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