Flash memory device having high speed erase mode and method for

Details Flash memory device having high speed erase mode and method for Flash memory device having high speed erase mode and method for

1994-10-11

1996-06-11

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular biasing

365218, G11C 1134

Patent

active

055263097

ABSTRACT:
A flash memory cell array MC having an array construction of a virtual grounding type wherein a column line B5 on one-end within the array MC is connected to a sense circuit AMP through a N-type MOSFET MV1. On erase verify, a column line B1 on another end is set to ground potential through an N-type MOSFETs MS1 and MS4. By selecting a row line W1, a current flowing from the column line B5 to the column B1 through memory elements M11 to M14 connected to the row line W1 is inspected by a sense circuit AMP, and the memory elements M11 to M14 are erase-verified at the same time.

REFERENCES:
patent: 5400286 (1995-03-01), Chu et al.
IEEE Solid-State Circuits Council "Journal of Solid-State Circuits", vol. 27, No. 11, (Special Issue on Memory and Logic), Nov., 1992.

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