Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2006-01-17
2006-01-17
Phung, Anh (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189080, C365S230060
Reexamination Certificate
active
06987704
ABSTRACT:
There is provided a synchronous memory device having a simplified data input unit for receiving and transferring data to an internal memory cell block, which is adapted to high frequency and can reduce a power consumption. The synchronous memory device includes: a data alignment unit for aligning in parallel a plurality of data sequentially inputted through one data input pin as many as the number of prefetched data to generate a plurality of aligned data; a global I/O line driving unit for receiving the plurality of aligned data and outputting the even data or the odd data to a memory core area in response to a data input strobe signal; a data input strobe signal generating unit for buffering the clock signal to output the data input strobe signal; and a data input strobe signal control unit for generating a data input strobe control signal used to allow the data input strobe signal generating unit to output the data input strobe signal only at a period when an operation corresponding to the write command is carried out.
REFERENCES:
patent: 6754133 (2004-06-01), Morita et al.
patent: 1020000013219 (2000-03-01), None
patent: 1020030008702 (2003-01-01), None
Blakely & Sokoloff, Taylor & Zafman
Hynix / Semiconductor Inc.
Luu Pho M.
Phung Anh
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