Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2006-05-09
2006-05-09
Fourson, George (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S379000, C438S262000, C438S257000, C438S264000, C438S129000, C438S599000, C438S424000, C438S238000, C438S536000
Reexamination Certificate
active
07042066
ABSTRACT:
A memory array dual-trench isolation structure and a method for forming the same have been provided. The method comprises: forming a p-doped silicon (p-Si) substrate; forming an n-doped (n+) Si layer overlying the p-Si substrate; prior to forming the n+ Si bit lines, forming a p+ Si layer overlying the n+ Si layer; forming a layer of silicon nitride overlying the p+ layer; forming a top oxide layer overlying the silicon nitride layer; performing a first selective etch of the top oxide layer, the silicon nitride layer, the p+ Si layer, and a portion of the n+ Si layer, to form n+ Si bit lines and bit line trenches between the bit lines; forming an array of metal bottom electrodes overlying a plurality of n-doped silicon (n+ Si) bit lines, with intervening p-doped (p+) Si areas; forming a plurality of word line oxide isolation structures orthogonal to and overlying the n+ Si bit lines, adjacent to the bottom electrodes, and separating the p+ Si areas; forming a plurality of top electrode word lines, orthogonal to the n+ Si bit lines, with an interposing memory resistor material overlying the bottom electrodes; and, forming oxide-filled word line trenches adjacent the word lines.
REFERENCES:
patent: 5238855 (1993-08-01), Gill
Hsu Sheng Teng
Pan Wei
Zhuang Wei-Wei
Fourson George
Maldonado Julio J.
Ripma David C.
Sharp Laboratories of America Inc.
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