Transistor with nanocrystalline silicon gate structure

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S185260, C438S257000, C438S261000, C438S264000, C977S723000, C977S763000

Reexamination Certificate

active

07110299

ABSTRACT:
A memory is described which has memory cells that store data using hot electron injection. The data is erased through electron tunneling. The memory cells are described as floating gate transistors wherein the floating gate is fabricated using a conductive layer of nanocrystalline silicon particles. Each nanocrystalline silicon particle has a diameter of about 10 Å to 100 Å. The nanocrystalline silicon particles are in contact such that a charge stored on the floating gate is shared between the particles. The floating gate has a reduced electron affinity to allow for data erase operations using lower voltages.

REFERENCES:
patent: 4688078 (1987-08-01), Hseih
patent: 5021999 (1991-06-01), Kohda et al.
patent: 5027171 (1991-06-01), Reedy et al.
patent: 5111430 (1992-05-01), Morie
patent: 5253196 (1993-10-01), Shimabukuro
patent: 5293560 (1994-03-01), Harari
patent: 5295095 (1994-03-01), Josephson
patent: 5317535 (1994-05-01), Talreja et al.
patent: 5388069 (1995-02-01), Kokubo
patent: 5424993 (1995-06-01), Lee et al.
patent: 5430670 (1995-07-01), Rosenthal
patent: 5434815 (1995-07-01), Smarandoiu et al.
patent: 5438544 (1995-08-01), Makino
patent: 5444303 (1995-08-01), Greenwood et al.
patent: 5467306 (1995-11-01), Kaya et al.
patent: 5477485 (1995-12-01), Bergemont et al.
patent: 5485422 (1996-01-01), Bauer et al.
patent: 5493140 (1996-02-01), Iguchi
patent: 5508543 (1996-04-01), Hartstein et al.
patent: 5511020 (1996-04-01), Hu et al.
patent: 5627781 (1997-05-01), Hayashi et al.
patent: 5670790 (1997-09-01), Katoh et al.
patent: 5714766 (1998-02-01), Chen et al.
patent: 5726070 (1998-03-01), Hong et al.
patent: 5754477 (1998-05-01), Forbes
patent: 5801401 (1998-09-01), Forbes
patent: 5852306 (1998-12-01), Forbes
patent: 5937295 (1999-08-01), Chen et al.
patent: 6114722 (2000-09-01), Jan et al.
patent: 6297095 (2001-10-01), Muralidhar et al.
patent: 6300193 (2001-10-01), Forbes
patent: 6344403 (2002-02-01), Madhukar et al.
patent: 6407424 (2002-06-01), Forbes
patent: 6912158 (2005-06-01), Forbes
Alivisatos, A. P., “Semiconductor Clusters, Nanocrystals, and quantum Dots”,Science, 271, (Feb. 16, 1996),933-937.
Alok, D., et al., “Electrical Properties of Thermal Oxide Grown on N-type 6H-Silicon Carbide”,Applied Physics Letters, 64, (May 23, 1994),2845-2846.
Baldwin, G. L., et al., “The Electronic Conduction Mechanism of Hydrogenated Nanocrystalline Silicon Films”,Proc. 4th Int. Conf. on Solid-State and Int. Circuit Tech, Beijing, (1995),66-68.
Bauer, M., et al., “A Multilevel-Cell 32 Mb Flash Memory”,Digest IEEE, Solid-State Circuits Conf.,,(1995),440.
Boeringer, Daniel W., et al., “Avalanche amplification of multiple resonant tunneling through parallel silicon microcrystallites”,Physical Rev. B, 51, (1995),13337-13343.
Demichelis, F., “Influence of Doping on the Structural and Optoelectronic Properties of Amorphous and Microcrystalline Silicon Carbide”,Journal of Applied Physics, 72(4), (Aug. 15, 1992),1327-1333.
Demichelis, F., “Physical Properties of Undoped and Doped Microcrystalline SiC:H Deposited By PECVD”,Materials Research Society Symposium Proceedings, 219, Anaheim, CA,(Apr. 30-May 3, 1991),413-418.
Dimaria, D. J., et al., “ced conduction and minimized charge trapping in electrically alterable only memories using off-stoichiometric silicon dioxide films”,J. Appl. Phys., vol. 55, No. 8, (Apr. 15, 1984),3000-3019.
Dipert, Brian, “Flash Memory Goes Mainstream”,IEEE Spectrum, 30(10), (Oct. 1993),48-52.
Dori, Leonello, et al., “Optimized Silicon-Rich Oxide (SRO) Deposition processfor 5-V-Only Flash EEPROM Applications”,IEEE Elect. Dev, Let. vol. 14, No. 6, (1993),283-285.
Edelberg, E., et al., “Visible Luminescence from Nanocrystalline silicon films produced by plasma enhanced chemical vapor deposition”,Appl. Phys. Lett., 68, (1996),1415-1417.
Hamakawa, Y., et al., “Optoelectronics and Photovoltaic Applications of Microcrystalline SiC”,Materials Research Society Symposium Proceedings, 164, Boston, MA,(Nov. 29-Dec. 1, 1989),291-301.
Hu, G., “Will Flash Memory Replace Hard Disk Drive?”,1994 IEEE International Electron Device Meeting, Panel Discussion, Session 24, Outline,(Dec. 1994), 2 pages.
Hybertsen, Mark S., “Absorption and Emission of Light in Nanoscale Silicon Structures”,Phys. Rev. Lett., 72, (1994),1514-1517.
Jung, Tae-Sung, et al., “A 3.3 V 128 Mb multi-level NAND flash memory for mass storage applications”,1996 IEEE International Solid-State Circuits Conference, 1996. Digest of Technical Papers. 43rd ISSCC., (1996),32-33,412.
Kamata, T., et al., “Substrate Current Due to Impact Ionization In MOS-FET”,Japan. J. Appl. Phys., 15, (Jun. 1976),1127-1134.
Kato, Masataka, et al., “Read-Disturb Degradation Mechanism due to Electron Trapping in the Tunnel Oxide for Low-voltage Flash Memories”,IEEE Electron Device Meeting, (1994),45-48.
Mori, Seiichi, et al., “Polyoxide Thinning Limitation and Superior ONO Interpoly Dielectric for Nonvolatile Memory Devices”,IEEE Trans. Elec. Dev. vol. 38, No. 2, (1991),270-277.
Ohkawa, M., et al., “A 98 mm2 3.3 V 64 Mb flash memory with FN-NOR type 4-level cell”,1996 IEEE International Solid-State Circuits Conference, 1996. Digest of Technical Papers. 43rd ISSCC., (1996),36-37.
Pan, Cheng-Sheng, et al., “A Scaling Methodology for Oxide-Nitride-Oxide Interpoly Dieelctric for EPROM Applications”,IEEE, Trans. Elect. Dev., vol. 37, No. 6, (1990),1439-1443.
Prendergast, Jim, “Flash or DRAM: Memory Choice for the Future”,IEEE Electron Device Meeting, Session 25, Phoenix, AZ,(1995).
Schoenfeld, O., et al., “Formation of Si Quantum dots in Nanocrystalline silicon”,Proc. 7th Int. Conf. on Modulated Semiconductor Structures, Madrid,, (1995),605-608.
Shen, S., et al., “Novel Self-Convergent Programming Scheme for Multi-Level P-Channel Flash Memory”,International Electron Devices Meeting, Technical Digest, Held in Washington, D.C.,(Dec. 7-10, 1997),287-290.
Shen, Shih-Jye, et al., “Ultra fast write speed, long refresh time, low power F-N operated volatile memory cell with stacked nanocrystalline Si film”,IEEE IEDM, (Dec. 8, 1996),515-518.
Shimabukuro, R. L., et al., “Circuitry for Artificial Neural Networks with Non-volatile Analog Memories”,IEEE Int'l Symp. on Circuits and Systems, 2, (1989),1217-1220.
Shimabukuro, R. L., et al., “Dual-Polarity Nonvolatile MOS Analogue Memory (MAM) Cell for Neural-Type Circuitry”,Electronics Lett., 24, (Sep. 15, 1988),1231-1232.
Suh, Kang-Deog, et al., “A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme”,IEEE J. Solid-State Circuits, 30, (Nov. 1995),1149-1156.
Sze, S. M., “Physics of Semiconductor Devices”,Wiley-Interscience 2d Ed., New York,(1981),482.
Takeuchi, K., et al., “A Double-Level-V Select Gate Array Architecture for Multilevel NANAD Flash Memories”,IEEE Journal of Solid-State Circuits, 31, (Apr. 1996),602-609.
Tiwari, Sandip, et al., “Volatile and Non-Volatile Memories in Silicon with Nano-Crystal Storage”,Int'l Electron Devices Meeting: Technical Digest, Washington, DC,(Dec. 1995),521-524.
Tsu, Raphael, et al., “Slow Conductance oscillations in nanoscale silicon clusters of quantum dots”,Appl. Phys. Lett., 65, (1994),842-844.
Tsu, R., et al., “Tunneling in Nanoscale Silicon Particles Embedded in an a-SiO2 Matrix”,Abstract, IEEE Device Research Conference, (1996),pp. 178-179.
White, W., et al., “Ion beam synthesis of nanocrystals and quantum dots in optical materials”,Proceedings of the 11th Int'l Conf. on ion implantation technology, (Jun. 16, 1996),824-827.
Yee, A., et al., “The Effect of Nitrogen on Pulsed Laser Deposition of Amorphous Silicon Carbide Films: Properties and Structure”,J. Materials Re

No affiliations

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Transistor with nanocrystalline silicon gate structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Transistor with nanocrystalline silicon gate structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Transistor with nanocrystalline silicon gate structure will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3586323

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.