Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Commitment control or register bypass
Reexamination Certificate
2006-01-17
2006-01-17
Kim, Kenneth S. (Department: 2111)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Commitment control or register bypass
C712S219000, C712S234000
Reexamination Certificate
active
06988187
ABSTRACT:
A method is provided for use in a processing pipeline operable to dispatch a plurality of instructions up to a first number of instructions per cycle to execution stages of the pipeline. According to such method, a skip instruction is decoded in a first cycle of the processing pipeline to determine a total number of subsequent instructions in the processing pipeline that are to be skipped. The skip instruction is executed in a second cycle. Subsequent instructions in the processing pipeline are prohibited from being executed, including prohibiting execution of a second number of instructions subsequent to the skip instruction in the second cycle, the second number being variable between zero and one less than the first number. Thereafter, if any subsequent instructions of the total number remain to be skipped, then a third number of instructions are prohibited from being executed in a third cycle subsequent to the second cycle, the third number being variable up to the lesser of: the number of subsequent instructions which remain to be skipped and the first number.
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patent: 5832260 (1998-11-01), Arora et al.
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Kim Kenneth S.
Sony Computer Entertainment Inc.
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