Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2006-01-03
2006-01-03
Tra, Quan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S158000
Reexamination Certificate
active
06982580
ABSTRACT:
A speed-locked loop (SLL) circuit to automatically determine overall chip speed, which is a function of the combination of supply voltage, temperature, and processing parameters, and to output the speed information in digital form to speed-compensating circuits in order to significantly reduce their sensitivity to operating conditions. Through negative feedback, a digitally controlled ring oscillator (DCO) is forced to lock at an oscillation frequency close to that specified by a six-bit speed constant input. A three-bit control bus varies the DCO oscillation frequency under digital control until the SLL achieves lock. When the SLL has achieved lock it latches the DCO control bus and outputs it as the speed information. The speed constant input may be varied under software control in order to determine the speed constant value that optimizes performance of speed-compensating circuits under SLL control.
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Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Tra Quan
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