Multi-level dither screening on a split arithmetic logic...

Details Multi-level dither screening on a split arithmetic logic... Multi-level dither screening on a split arithmetic logic...

2006-03-14

2006-03-14

Poon, King Y. (Department: 2624)

Facsimile and static presentation processing

Static presentation processing

Attribute control

C358S001900, C358S003200, C358S003140, C358S003010, C358S003210

Reexamination Certificate

active

07012717

ABSTRACT:
This invention is a method of multilevel dither screening in a printer. Plural pixel values are packed into equal sections of a first data word. Corresponding dither values are packed into the equal sections of a second data word. These first and second data words are added in an arithmetic logic unit selectively spilt into the equal sections. Each section of the sum data word is saturated to all 1's. A predetermined number of least significant bits of the saturated sections are truncated. The resulting normalized pixel values are quantized into a limited set of threshold ranges. This dithering process serves to introduce an amount of scattering to the input pixel values to reduce quantization and pixelation artifacts in the final printed product.

REFERENCES:
patent: 5606677 (1997-02-01), Balmer et al.
patent: 5687087 (1997-11-01), Taggart
patent: 5912745 (1999-06-01), Ulichney

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