Semiconductor memory device having improved error correcting cir

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371 401, 371 211, 365200, H03M 1300

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051950995

ABSTRACT:
A semiconductor memory device having an error correcting circuit includes a circuit for generating a desired test signal with which memory cells used for error correction are to be tested, and another circuit for judging on an chip-basis whether memory cells of the semiconductor memory device are normal or not. The memory cells for error correction can be tested accurately by application of desired test signal. In addition, since there is no necessity of provision of a circuit for comparing externally applied data and data delivered from the semiconductor memory device, a test can be preformed readily.

REFERENCES:
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patent: 4531213 (1985-07-01), Scheuneman
patent: 4612630 (1986-09-01), Rosier
patent: 4730320 (1988-03-01), Hidaka
patent: 4794597 (1988-12-01), Ooba
patent: 4878220 (1989-10-01), Hashimoto
patent: 4958324 (1990-09-01), Devin
patent: 4967415 (1990-10-01), Tanagawa
H. Davis, "A 70-ns Word-Wide 1-Mbit ROM With On-Chip Error-Correction Circuits" IEEE Journal of Solid-State Circuits, vol. SC-20, No. 5 (Oct. 1985), pp. 958-963.
Memory Data book, Mitsubishi (1982), pp. 4-41-4-47.

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