Computation of sign bit and sign extension in the partial produc

Details Computation of sign bit and sign extension in the partial produc Computation of sign bit and sign extension in the partial produc

1992-03-31

1993-03-16

Nguyen, Long T.

Boots, shoes, and leggings

G06F 738

Patent

active

051950510

ABSTRACT:
An arithmetic logic for selectively multiplying either floating point numbers and unsigned integers or signed integers. A signed integer request signal has a first state indicating a floating point or unsigned integer operation and a second state indicating a signed integer operation. A multiplicand operand includes a most significant bit (MSB) of the multiplicand. A Booth encoder provides at an output of the Booth encoder a booth encoded set having a plurality of bits, including a most significant bit (MSB) of the booth encoded set. A partial product generator connected to the multiplicand operand and to the Booth encoder output generates a plurality of partial products. A carry save adder (CSA) connected to the partial product generator generates a sum vector and a carry vector. An exclusive OR has one input connected to the MSB of the Booth encoded set and another input connected to the MSB of the multiplicand. A 2:1 MUX is connected to the MSB of the Booth encoded set and to the exclusive OR. The signal integer request signal input to the MUX selects the MSB of the Booth encoded set upon the condition that the signal integer request signal is in the first state and for selects the output of the exclusive OR upon the condition that the signed integer request signal is in the second state.

REFERENCES:
patent: 4748582 (1988-05-01), New et al.
patent: 5038315 (1991-08-01), Rao
patent: 5144576 (1992-09-01), Briggs et al.

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