Static information storage and retrieval – Powering
Reexamination Certificate
2006-04-11
2006-04-11
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Powering
C365S154000, C326S093000, C326S044000
Reexamination Certificate
active
07027345
ABSTRACT:
Techniques, including a system and method, are disclosed for conditionally pre-charging a memory circuit, for example a flip-flop, and thus reducing power consumption. In an embodiment a method for reducing power consumption in a memory circuit, including, a pre-charged stage coupled to an evaluation stage by at least an internal node, is provided. The method includes setting an input of the pre-charged stage to a first high logic level. Next, responsive to the setting of the input, the internal node is set to a low logic level within a first transparency window. Then responsive to the setting of the internal node, the evaluation stage changes the output of the evaluation stage to a second high logic level within the first transparency window. Lastly, when the input remains at the first high-logic level, the internal node is maintained at the low logic level through at least a second transparency window.
REFERENCES:
patent: 5764089 (1998-06-01), Partovi et al.
patent: 5774005 (1998-06-01), Partovi et al.
patent: 5898330 (1999-04-01), Klass
patent: 5917355 (1999-06-01), Klass
patent: 5990717 (1999-11-01), Partovi et al.
patent: 6060909 (2000-05-01), Aipperspach et al.
patent: 6087872 (2000-07-01), Partovi et al.
patent: 6201415 (2001-03-01), Manglore
patent: 6646487 (2003-11-01), Nedovic et al.
patent: 6693459 (2004-02-01), Nedovic et al.
H. Partovi et al., “Flow-Through Latch and Edge-Triggered Flip-Flop Hybrid Elements”, 1996 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC, San Francisco, CA, USA, Feb. 8-10, 1996.
B.S. Kong, S.-S Kim, Y.-H. Jun, “Conditional-Capture Flip-Flop Terchnique for Statistical Power Reduction” 2000 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 290-291, Feb. 2000.
F. Klass, “Semi-Dynamic and Dynamic Flip-Flops with Embedded Logic”, Symp. on VLSI Circ. Digest of Technical Papers, Jun. 1998.
J. Yuan, C. Svensson, “High-Speed CMOS Circuit Technique”, IEEE Journal of Solid-State Circuits, vol. 24, (No. 1), pp. 62-70, Feb. 1, 1989.
N. Nedovic, V. G. Oklobdzija, “Hybrid Latch Flip-Flop with Improved Power Efficiency”, Proceedings of Symposium on Integrated Circuits and Systems Design, pp. 211-215, 2000.
Nedovic Nikola
Oklobd{hacek over (z)}ija Vojin G.
Walker William W.
Le Vu A.
Sheppard Mullin Richter & Hampton LLP
LandOfFree
Conditional pre-charge method and system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Conditional pre-charge method and system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Conditional pre-charge method and system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3557057