Low profile stacked multi-chip package and method of forming...

Details Low profile stacked multi-chip package and method of forming... Low profile stacked multi-chip package and method of forming...

2006-03-07

2006-03-07

Clark, S. V. (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S686000

Reexamination Certificate

active

07009300

ABSTRACT:
A stacked multi-chip package includes first chip with conductive pads on both front and back sides. The front side may include a polymer layer with interconnect. A first polymer layer formed on the backside of the first chip has a cutout to receive a second chip. The first and second chip may be joined as a flip chip. A second polymer layer formed on the first polymer layer has a cutout to receive a third chip. A third polymer layer formed on the second polymer layer contains interconnect to interconnect the first, second and third chips, including the backside of the first chip. Conductive bumps on the front side of the first chip and on the polymer layers provide external I/O connection.

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