Method and architecture for controlling asymmetry of an LMS...

Details Method and architecture for controlling asymmetry of an LMS... Method and architecture for controlling asymmetry of an LMS...

2006-07-11

2006-07-11

Ngo, Chuong D. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07076513

ABSTRACT:
A circuit (48) and method, which can be used in a mass data storage device, controls adaptation asymmetry of coefficients of an FIR filter (20) using an accumulator (52) or accumulating correlation results between unequalized FIR filter input data samples and FIR filter output equalized error samples. A circuit (52) generates coefficient increment and decrement requests from the accumulated correlation results. A circuit (120,102′,122) updates the coefficients within a symmetric coefficient pair on the basis of the increment and decrement requests only if a predetermined nonzero coefficient magnitude difference between the coefficient pair would not be exceeded by the update. In one embodiment of the invention, circuit (52) and method are provided for generating coefficients for an FIR filter in a sign-sign LMS algorithm using an accumulator for accumulating in a sub-least significant bit register (54) successive sign values of an error between input data samples to the FIR filter and output error samples from the FIR filter and an increment/decrement circuit (64) to request an increment/decrement of a coefficient value of the FIR flter on the basis of carry-out and borrow-in operations of the sub-least significant bit register (54).

REFERENCES:
patent: 5590154 (1996-12-01), Forni et al.
patent: 5650954 (1997-07-01), Minuhin
patent: 5793820 (1998-08-01), Vander Mey
patent: 5887059 (1999-03-01), Xie et al.
patent: 6222879 (2001-04-01), Cideciyan et al.

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