Carry foreknowledge adder

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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Reexamination Certificate

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07111034

ABSTRACT:
A carry foreknowledge adder comprise an adding circuit for adding binary numbers A and B of n bits; and a plurality of carry foreknowledge circuit blocks that respectively corresponding to divisional portions obtained by dividing the A and the B through setting a unit length. Each carry foreknowledge circuit block has a plurality of arithmetic operating portions (j, i) in correspondence to each bit, that respectively receive a block carry Cincorresponding to the most significant bit in a lower the carry foreknowledge circuit block from the lower carry foreknowledge circuit block corresponding to lower divisional portion, each arithmetic operating portion arithmetically determining the carry Cion the basis of the block carry Cin, and outputting the carry Cito the adding circuit, and each arithmetic operating portion (j, i) has a logic circuit portion which receives the block carry Cinand is arranged on an output terminal side.

REFERENCES:
patent: 4764886 (1988-08-01), Yano
patent: 4956802 (1990-09-01), Priem
patent: 5257218 (1993-10-01), Poon
patent: 5337269 (1994-08-01), McMahan et al.
patent: 5375081 (1994-12-01), Anderson
patent: 5581497 (1996-12-01), Kumar
patent: 6205463 (2001-03-01), Manglore et al.
patent: 2003/0115237 (2003-06-01), Fletcher

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