System and method for aligning internal transmit and receive...

Details System and method for aligning internal transmit and receive... System and method for aligning internal transmit and receive...

2006-01-17

2006-01-17

Corrielus, Jean B. (Department: 2637)

Pulse or digital communications

Synchronizers

C370S503000, C327S141000

Reexamination Certificate

active

06987823

ABSTRACT:
A circuit defining a second system clock in a system comprising a master connected to one or more slave devices via a channel, the channel communicating an externally generated first system clock towards the master. The circuit comprising a delay locked loop circuit configured to receive the first system clock and a second phase feedback signal as inputs and to generate a transmit clock signal. A 90 degrees block configured to receive the transmit system clock and to generate a 90 degrees phased shifted version of the transmit clock signal. An output driver circuit configured to receive the 90 degrees phased shifted version of the transmit clock signal and to generate the second system clock. A first phase detector configured to receive a receive system clock and the transmit system clock and to generate a first phase feedback signal. A delay element configured to receive the first system clock and the first phase feedback signal and to generate a delayed first system clock. A second phase detector configured to receive the delayed first system clock and the second system clock and to generate the second phase feedback signal.

REFERENCES:
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patent: 5953286 (1999-09-01), Matsubara et al.
patent: 6289068 (2001-09-01), Hassoun et al.
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patent: 6469699 (2002-10-01), Yoshine
patent: 6487648 (2002-11-01), Hassoun
patent: 2001/0033630 (2001-10-01), Hassoun et al.

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