Electrical computers and digital processing systems: processing – Processing architecture – Superscalar
Reexamination Certificate
2006-04-11
2006-04-11
Donaghue, Larry D. (Department: 2154)
Electrical computers and digital processing systems: processing
Processing architecture
Superscalar
C712S217000, C712S218000
Reexamination Certificate
active
07028161
ABSTRACT:
The high-performance, RISC core based microprocessor architecture includes an instruction fetch unit for fetching instruction sets from an instruction store and an execution unit that implements the concurrent execution of a plurality of instructions through a parallel array of functional units. The fetch unit generally maintains a predetermined number of instructions in an instruction buffer. The execution unit includes an instruction selection unit, coupled to the instruction buffer, for selecting instructions for execution, and a plurality of functional units for performing instruction specified functional operations. A unified instruction scheduler, within the instruction selection unit, initiates the processing of instructions through the functional units when instructions are determined to be available for execution and for which at least one of the functional units implementing a necessary computational function is available. Unified scheduling is performed across multiple execution data paths, where each execution data path, and corresponding functional units, is generally optimized for the type of computational function that is to be performed on the data: integer, floating point, and boolean. The number, type and computational specifics of the functional units provided in each data path, and as between data paths, are mutually independent.
REFERENCES:
patent: 3346851 (1967-10-01), Thornton et al.
patent: 3771138 (1973-11-01), Celtruda et al.
patent: 4128880 (1978-12-01), Cray, Jr.
patent: 4200927 (1980-04-01), Hughes et al.
patent: 4296470 (1981-10-01), Fairchild et al.
patent: 4410939 (1983-10-01), Kawakami
patent: 4434641 (1984-03-01), Nguyen
patent: 4459657 (1984-07-01), Murao
patent: 4626989 (1986-12-01), Torii
patent: 4675806 (1987-06-01), Uchida
patent: 4722049 (1988-01-01), Lahti
patent: 4752873 (1988-06-01), Shonai et al.
patent: 4807115 (1989-02-01), Torng
patent: 4811208 (1989-03-01), Myers et al.
patent: 4901233 (1990-02-01), Liptay
patent: 4928226 (1990-05-01), Kamada et al.
patent: 4942525 (1990-07-01), Shintani et al.
patent: 5003462 (1991-03-01), Blaner et al.
patent: 5129067 (1992-07-01), Johnson
patent: 5134561 (1992-07-01), Liptay
patent: 5136697 (1992-08-01), Johnson
patent: 5185872 (1993-02-01), Arnold et al.
patent: 5226126 (1993-07-01), McFarland et al.
patent: 5226166 (1993-07-01), Ishida et al.
patent: 5493687 (1996-02-01), Garg et al.
patent: 5560035 (1996-09-01), Garg et al.
patent: 5561776 (1996-10-01), Popescu et al.
patent: 5564117 (1996-10-01), Lentz et al.
patent: 5574927 (1996-11-01), Scantlin
patent: 5574941 (1996-11-01), Horst
patent: 5592636 (1997-01-01), Popescu et al.
patent: 5625837 (1997-04-01), Popescu et al.
patent: 5627983 (1997-05-01), Popescu et al.
patent: 5640588 (1997-06-01), Vegesna et al.
patent: 5682546 (1997-10-01), Garg et al.
patent: 5708841 (1998-01-01), Popescu et al.
patent: 5768575 (1998-06-01), McFarland et al.
patent: 5778210 (1998-07-01), Henstrom et al.
patent: 5797025 (1998-08-01), Popescu et al.
patent: 5832205 (1998-11-01), Kelly et al.
patent: 5832292 (1998-11-01), Nguyen et al.
patent: 5832293 (1998-11-01), Popescu et al.
patent: 5838986 (1998-11-01), Garg et al.
patent: 6038653 (2000-03-01), Nguyen et al.
patent: 6044449 (2000-03-01), Garg et al.
patent: 6047348 (2000-04-01), Lentz et al.
patent: 6128723 (2000-10-01), Nguyen et al.
patent: 6249856 (2001-06-01), Garg et al.
patent: 0 136 179 (1985-04-01), None
patent: 0 171 595 (1986-02-01), None
patent: 0 354 585 (1990-02-01), None
patent: 0 368 332 (1990-05-01), None
patent: 0 372 751 (1990-06-01), None
patent: 0 377 991 (1990-07-01), None
patent: 0 402 856 (1990-12-01), None
patent: 0 419 105 (1991-03-01), None
patent: 0 426 393 (1991-05-01), None
patent: 0 479 390 (1992-04-01), None
patent: 2 575 564 (1986-07-01), None
patent: 2 011 682 (1979-07-01), None
patent: 61-107434 (1986-05-01), None
patent: 63-136138 (1988-06-01), None
patent: 63-172343 (1988-07-01), None
patent: 63-318634 (1988-12-01), None
patent: 64-36336 (1989-02-01), None
patent: 2-22736 (1990-01-01), None
patent: 2-48732 (1990-02-01), None
patent: 2-87229 (1990-03-01), None
patent: 2-130634 (1990-05-01), None
patent: 2-130635 (1990-05-01), None
patent: 2-211534 (1990-08-01), None
patent: 3-34024 (1991-02-01), None
patent: 3-35322 (1991-02-01), None
patent: 3-141429 (1991-06-01), None
patent: 3-147134 (1991-06-01), None
patent: 3-218524 (1991-09-01), None
patent: 4-54638 (1992-02-01), None
patent: 4-96132 (1992-03-01), None
patent: 4-503582 (1992-06-01), None
patent: 6-19707 (1994-01-01), None
patent: 6-501805 (1994-01-01), None
patent: 6-501122 (1994-02-01), None
patent: 6-501123 (1994-02-01), None
patent: 6-501586 (1994-02-01), None
patent: 6-502034 (1994-03-01), None
patent: 6-502035 (1994-03-01), None
Bakoglu et al. The IBM RISC System/6000 processor: Hardware overview, Jan. 1990.
Hara et al., “Branch Pipeline of DSNS Superscalar Processor Prototype”,Computer Architecture, 86-3, Jan. 24, 1991, pp 1-8 in Japanese language (with English language translation 20 pages).
Kohn, Les, et al., “Introducing the Intel i860 64-Bit Mircoprocessor,” IEEE Micro, vol. 9, No. 4, Aug. 1989, pp. 15-30.
Adams, R. G., et al., “Utilising Low Level Parallelism in General Purpose Code: The HARP Project,” Microprocessing and Microprogramming, vol. 29, No. 3, Oct. 1990, pp. 137-149.
Charles Melear, Motorola, Inc., The Design of the 88000 RISC Family, IEEE Micro, vol. 9, No. 2, Apr. 1989, Los Alamitos, CA, U.S., pp. 26-38.
Patent Abstracts of Japan, vol. 010, No. 089, Apr. 1986, & JP, A, 60 225 943 (Hitachi Seisakusho K K) Nov. 11, 1985.
Smith et al., Implementing Precise Interrupts in Pipelined Processors, IEEE Transactions on Computers, vol. 37, No. 5, May 1988, New York, U.S., pp. 562-573.
IBM Technical Disclosure Bulletin, vol. 28, No. 6, Nov. 1985, Overlap of Store Multiple Operation with Suceeding Operations through Second Set of General Purpose Registers.
Molnar et al., “Floating-Point Processor,” 1989 IEEE.
Adams et al., “Utilizing Low Level Parallelism in General Purpose Code: The HARP Project,” Oct. 1990.
Bakoglu et al., “IBM Second-Generation RISC Machine Organization,” IEEE, 1990.
Intrater et al., “A Superscalar Microprocessor,” IEEE, Mar. 1991.
Oehler et al., “IBM RISC System/6000: Architecture and Performance,” Jun. 1991.
Goss, “Motorola's 8800 Integration Performance and Application,” 1989, IEEE.
Popescu et al., The Metaflow Architecture, Metaflow Technologies, Inc., Jun. 1991.
Weiss,R., “The Third-Generation RISC Processors,” On Special Report,Mar. 30, 1992, pp. 96-108.
Johnson, Superscalar Microprocessor Design, Prentice-Hall, Inc., 1991, (in its entirety).
Hennessy et al., Computer Architecture-A Quantitative Approach, Morgan Kaufmann Publishers, Inc., 1990 (in its entirety).
Fairchild Semiconductor Corporation, CLIPPER™ 32-Bit Microprocessor User's Manual, Prentice-Hall, 1987, Chapter 1 and Section 3. 5.
Hwu et al., “Design Choices for the HPSM Microprocessor Chip,” Proceedings of the Twentieth Annual Int'l Conference on System Schemes, 1987, pp. 330-336.
Uvieghara et al., “An On-Chip Smart Memory for a Data-Flow CPU,” IEEE Journal of Solid-State Circuits, vol. 25, No. 1,Feb. 1990, pp. 84-94.
Patt et al., “HPS, A New Microarchitecture: Rationale and Introduction,” Computer Science Division, University of California, Berkeley, 1985.
Uvieghara et al., “An Experimental Single-Chip Data FlowCPU,” 1990 Symposium on VLSI Circuits, Digest of Technical Papers (Cat. N. 90CH2885-2), IEEE, New York, pp. 119-120.
Smith, M.D., et al., “Boosting Beyond Static Scheduling in a Superscalar Processor,” IEEE, 1990, pp. 344-354.
Murakami, K. et al., “SIMP (Single Instruction Stream/Multiple Instruction Pipelining) : A Novel High-Speed Single-Processor Architecture,” ACM, 1989, pp. 78-85.
Jouppi, N.P., “The Nonuniform Distribution of Instruction-Level and Machine Parall
Garg Sanjiv
Hagiwara Yasuaki
Lau Te-Li
Lentz Derek J.
Miyayama Yoshiyuki
Donaghue Larry D.
Seiko Epson Corporation
Sterne Kessler Goldstein & Fox PLLC
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