Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2006-07-11
2006-07-11
Ferris, Fred (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S013000, C703S014000, C703S016000, C703S002000, C716S030000, C716S030000, C716S030000, C717S141000
Reexamination Certificate
active
07076416
ABSTRACT:
A method for evaluating a logic state of a design node involves compiling a logic design to generate an annotated symbol table and a levelized design, obtaining a logic evaluation cost from the levelized design, locating a strategic node using the logic evaluation cost, marking the strategic node, and computing the logic state of the design node using the annotated symbol table, the strategic node, and the levelized design.
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Chen Liang T.
Lam William kwei-cheung
McWilliams Thomas M.
Ferris Fred
Osha & Liang LLP
Sun Microsystems Inc.
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