Dynamical adaptation of memory sense electronics

Static information storage and retrieval – Addressing – Sync/clocking

Reexamination Certificate

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C365S205000, C365S233500

Reexamination Certificate

active

07079447

ABSTRACT:
A circuit and a method are given, to realize a dynamically adapting response speed behavior of memory sense electronics for Sense Electronics Endowed (SEE) memory devices. Fast memories use sense amplifiers in the read path in order to react fast with the data being delivered from a given address position. In order to achieve short response times, these sense amplifiers are normally responding very fast with accordingly high power consumption. Dynamically reducing the response speed after a certain “on” time of operation will save power for fast memories used in conditions where the utmost speed is not needed. Said circuit and method are designed in order to be implemented with a very economic number of components, capable to be realized with modern integrated circuit technologies.

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Co-pending U.S. Patent App. Pub. DS-04-017, U.S. Appl. No. 10/898,478, filed Jul. 23, 2004, “Dynamical Biasing of Memory Sense Amplifiers”.
“A 36n 1Mbit CMOS EPROM with new data sensing technique,” by Nakai et al., 1990 Symp. on VLSI Circuits, IEEE 1990, XP-002322527, pp. 95-96.

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