Member and member manufacturing method

Active solid-state devices (e.g. – transistors – solid-state diode – Bulk effect device – Bulk effect switching in amorphous material

Reexamination Certificate

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Details

C257S048000, C438S445000, C438S456000, C438S457000, C438S458000, C438S459000, C438S014000

Reexamination Certificate

active

07049624

ABSTRACT:
A porous structure with high uniformity is provided even when evaluated at a high resolution (high evaluation standard) of several or several ten nm or less. By applying this porous structure to the manufacture of an SOI substrate, an SOI substrate which has an SOI layer with a small number of defects is provided. In a region at a depth of 5 to 10 nm from the surface of a porous Si layer, values of parameters such as porosity and the like which represent a porous structure are uniformed. The manufacture of an SOI substrate using this porous Si layer reduces recessed defects in an SOI layer.

REFERENCES:
patent: 5371037 (1994-12-01), Yonehara
patent: 5854123 (1998-12-01), Sato et al.
patent: 5856229 (1999-01-01), Sakaguchi et al.
patent: 6150031 (2000-11-01), Yonehara
patent: 2001/0019153 (2001-09-01), Sato et al.
patent: 2002/0016167 (2002-02-01), Fossati et al.
patent: 2003/0190794 (2003-10-01), Ohmi et al.
patent: 05-21338 (1993-01-01), None
patent: 05-21371 (1993-01-01), None
patent: 7-45573 (1995-02-01), None
patent: 08-306682 (1996-11-01), None
St. Frohnhoff et al., “Formation Techniques for Porous Silicon Superlattices”, Thin Solid Films, vol. 255 (1995), pp. 59-62.

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