Multiple configuration multiple chip memory device and method

Details Multiple configuration multiple chip memory device and method Multiple configuration multiple chip memory device and method

Filed on

2006-01-03

Date issued

2006-01-03

Examiner

Phung, Anh (Department: 2824)

Patent Class

Static information storage and retrieval

SubClass

Addressing

SubSubClass

Plural blocks or banks

Other Related Categories

C365S230080

Type

Reexamination Certificate

Status

active

Patent number

06982921

Description

ABSTRACT:
A memory integrated circuit can be used either alone or as a pair to provide a memory device having twice the capacity of the single integrated circuit. The larger capacity memory device is addressed using an extra row address bit. The extra row address bit is used either to alternately enable each of the memory integrated circuits in one configuration or is remapped to become an extra column address bit in another configuration.

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