Integrated circuit and method for interfacing two voltage...

Details Integrated circuit and method for interfacing two voltage... Integrated circuit and method for interfacing two voltage...

2005-08-09

2005-08-09

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S333000, C327S551000

Reexamination Certificate

active

06927616

ABSTRACT:
An integrated circuit designed to reduce on-chip noise coupling. In one embodiment, circuit (60) includes the following: a circuit transformer (62) capable of converting a noise sensitive input reference clock signal to an output signal having a voltage compatible with a predetermined sink voltage logic level; and a biased receiver network (64) having a PFET current mirror (74) coupled with a NFET current (72), the biased receiver transistor network designed to multiply the transformer signal to offset a mutual coupling loss of the transformer. In at least one alternative embodiment, the input reference clock signal originates at an off-chip clock generator circuit (42) and the output signal from receiver (64) is input to a PLL (44). In another alternative embodiment, the transformer is a monolithic integrated transformer. Another alternative embodiment of the present invention is a method of reducing on-chip noise coupling.

REFERENCES:
patent: 5966297 (1999-10-01), Minegishi
patent: 6008681 (1999-12-01), Beutler et al.
patent: 6087861 (2000-07-01), Cranford et al.
patent: 6359492 (2002-03-01), Hipp

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