Semidigital delay-locked loop using an analog-based finite...

Details Semidigital delay-locked loop using an analog-based finite... Semidigital delay-locked loop using an analog-based finite...

2005-08-09

2005-08-09

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S158000

Reexamination Certificate

active

06927611

ABSTRACT:
A low-power full-rate semidigital DLL architecture using an analog-based FSM (AFSM). The AFSM is a mixed-mode FSM in which analog integration is substituted for digital filtering, thus enabling a lower power implementation of the clock and data recovery function. An integrated voltage is converted to a digital code by an analog-to-digital converter (ADC), and the digital code is used either directly or after (low frequency) digital signal processing to control a controllable delay element, such as, a phase rotator, for data edge tracking.

REFERENCES:
patent: 6043717 (2000-03-01), Kurd
patent: 6650157 (2003-11-01), Amick et al.
Sidiropoulos et al., “A Semidigital Dual Delay-Locked Loop”, IEEE Journal of Solid-State Circuits, vol. 32, No. 11, Nov. 1997, pp. 1683-1692.

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