Fishing – trapping – and vermin destroying
Patent
1995-06-08
1996-06-11
Quach, T. N.
Fishing, trapping, and vermin destroying
437186, 437193, 437195, H01L 21336
Patent
active
055255523
ABSTRACT:
A process for fabricating MOSFET devices, using an optimized buried contact approach, has been developed. The process includes the provision of thermal oxide (10) and polysilicon spacer (12) adjacent polysilicon buried contact (7) and gate (4). This process is forgiving for non-optimized photolithographic alignments, which when used as masks for dry etching, can result in the creation of trenches or crevices in the device region, to a polysilicon contact structure. Films used to create the spacer sidewalls on polysilicon gate structures, also fill the unwanted trench or crevice. Therefore materials, such as silicon nitride and tantalum oxide are chosen, that will result in the creation of a more conductive contact path, between the buried contact region and a polysilicon contact structure, due to the accumulation layer formed below these sidewall spacer materials.
REFERENCES:
patent: 4341009 (1982-07-01), Bartholomew et al.
patent: 5134085 (1992-07-01), Gilgen et al.
patent: 5234858 (1993-08-01), Fazan et al.
patent: 5272099 (1993-12-01), Chou et al.
patent: 5318925 (1994-06-01), Kim
patent: 5358903 (1994-10-01), Kim
patent: 5376577 (1994-12-01), Roberts et al.
patent: 5413961 (1995-05-01), Kim
Quach T. N.
Saile George O.
Taiwan Semiconductor Manufacturing Company
LandOfFree
Method for fabricating a MOSFET device with a buried contact does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating a MOSFET device with a buried contact, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating a MOSFET device with a buried contact will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-351523