Method for reducing dopant diffusion

Details Method for reducing dopant diffusion Method for reducing dopant diffusion

1994-11-16

1996-06-11

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437976, 148DIG7, H01L 21266

Patent

active

055255299

ABSTRACT:
A process is disclosed for inhibiting undesired diffusion of implanted dopants during and after dopant activation, as can occur during source/drain anneal. Undesired dopant diffusion is minimized by a dopant blocking layer, which is applied to the semiconductor body prior to dopant activation, and preferably prior to dopant implantation. The composition of the blocking layer is selected in accordance with the diffusion mechanism of the dopant to be implanted so that the concentration of lattice vacancies or interstitials (depending upon the dopant diffusion mechanism) is reduced, thereby inhibiting undesired migration of the implanted species.

REFERENCES:
patent: 3945856 (1976-03-01), Koenig et al.
patent: 4843023 (1989-06-01), Chiu et al.
Ahn, S. T., et al, Reduction of Lateral Phosphorus in CMOS n-Wells, IEEE Transactions on Electron Devices, vol.37 No. 3, Mar. 1990, pp. 806-807.
Wong, S. S. and Ekstedt, T. W., CMOS Well Drive-In in NH.sub.3 for Reduced Lateral Diffusion and Heat Cycle, IEEE Electron Device Letters, vol., EDL-6, No. 12, Dec. 1985, pp. 659-661.
Ghardhi, "VLSI Fabrication Principles", 1983, pp. 113-118, 325-328, 353-354, 372-373, 420-424, 427-429.

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