Predecode column architecture and method

Details Predecode column architecture and method Predecode column architecture and method

Filed on

2005-12-06

Date issued

2005-12-06

Examiner

Phung, Anh (Department: 2824)

Patent Class

Static information storage and retrieval

SubClass

Addressing

SubSubClass

Particular decoder or driver circuit

Other Related Categories

C365S230080, C365S230090, C365S189050

Type

Reexamination Certificate

Status

active

Patent number

06973006

Description

ABSTRACT:
A system and method for predecoding memory addresses by generating a sequence of predecode signals based on the memory address, providing the sequence of predecode signals as a first set of activation signals, and based on the value of the memory address, either resequencing the sequence of predecode signals and providing the resequenced predecode signals as a second set of activation signals or providing the sequence of predecode signals as the second set of activation signals.

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Choi, Y. et al., “16-Mb Synchronous DRAM with 125-Mbyte/s Data Rate”, IEEE Journal of Solid-State Circuits, vol. 29, No. 4, Apr. 1994, pp. 529-533.
Sunaga, T. et al., “A Full Bit Prefetch Architecture for Synchronous DRAM's”, IEEE Journal of Solid-State Circuits, vol. 30, No. 9, Sep. 1995, pp. 998-1005.

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