Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
2005-11-08
2005-11-08
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S673000, C257S668000, C257S678000, C257S691000, C257S698000, C257S730000, C257S734000, C257S737000, C257S738000, C257S784000, C257S786000, C257S787000
Reexamination Certificate
active
06963127
ABSTRACT:
Protective structures for bond wires or other intermediate conductive elements of a semiconductor device assembly cover the intermediate conductive elements without covering a substantial portion of a semiconductor device from which the intermediate conductive elements extend. In addition to coating at least portions of one or more intermediate conductive elements, the protective structure may include a fence which is configured to receive a semiconductor device. Such a fence may be formed integrally with the remainder of the protective structure or a separately formed member. The protective structures may be formed from a photopolymer material which has been at least partially cured, for example, by stereolithography processes. Accordingly, the protective structures may include a single layer or a plurality of superimposed, contiguous, mutually adhered layers.
REFERENCES:
patent: 3753046 (1973-08-01), Towell
patent: 3777221 (1973-12-01), Tatusko et al.
patent: 4424089 (1984-01-01), Sullivan
patent: 4528259 (1985-07-01), Sullivan
patent: 4582778 (1986-04-01), Sullivan
patent: 4610941 (1986-09-01), Sullivan
patent: 4618567 (1986-10-01), Sullivan
patent: 4645733 (1987-02-01), Sullivan
patent: 4706167 (1987-11-01), Sullivan
patent: 4752553 (1988-06-01), Sullivan
patent: 4756929 (1988-07-01), Sullivan
patent: 4775611 (1988-10-01), Sullivan
patent: 4971895 (1990-11-01), Sullivan
patent: 5014161 (1991-05-01), Lee et al.
patent: 5173220 (1992-12-01), Reiff et al.
patent: 5200026 (1993-04-01), Okabe
patent: 5264061 (1993-11-01), Juskey et al.
patent: 5278442 (1994-01-01), Prinz et al.
patent: 5354593 (1994-10-01), Grandmont et al.
patent: 5457341 (1995-10-01), West
patent: 5457878 (1995-10-01), Rostoker et al.
patent: 5484314 (1996-01-01), Farnworth
patent: 5559444 (1996-09-01), Farnworth et al.
patent: 5561328 (1996-10-01), Massingill et al.
patent: 5705117 (1998-01-01), O'Connor et al.
patent: 5739585 (1998-04-01), Akram et al.
patent: 5739588 (1998-04-01), Ishida et al.
patent: 5773320 (1998-06-01), Bayerer
patent: 6039898 (2000-03-01), Glushko
patent: 6154940 (2000-12-01), Onishi et al.
patent: 6251488 (2001-06-01), Miller et al.
patent: 6259962 (2001-07-01), Gothait
patent: 6268584 (2001-07-01), Keicher et al.
patent: 6309729 (2001-10-01), Glushko et al.
patent: 6325961 (2001-12-01), Beers et al.
patent: 6337122 (2002-01-01), Grigg et al.
patent: 6376769 (2002-04-01), Chung
patent: 6391251 (2002-05-01), Keicher et al.
patent: 6468891 (2002-10-01), Williams
patent: 6500746 (2002-12-01), Williams
patent: 6524346 (2003-02-01), Farnworth
patent: 6529027 (2003-03-01), Akram et al.
patent: 6531335 (2003-03-01), Grigg
patent: 6544902 (2003-04-01), Farnworth
patent: 6630730 (2003-10-01), Grigg
patent: 6632732 (2003-10-01), Williams
patent: 6634100 (2003-10-01), Akram et al.
patent: 2002/0102829 (2002-08-01), Williams
patent: 2002/0111003 (2002-08-01), Williams
patent: 2002/0123213 (2002-09-01), Williams
patent: 2002/0171177 (2002-11-01), Kritchaman et al.
patent: 2003/0045047 (2003-03-01), Williams
patent: 2003/0068840 (2003-04-01), Grigg
patent: 2003/0098470 (2003-05-01), Williams
patent: 2003/0102566 (2003-06-01), Farnworth
patent: 2003/0111727 (2003-06-01), Kurusu
patent: 2003/0141885 (2003-07-01), Akram et al.
patent: 2003/0151167 (2003-08-01), Kritchman et al.
Miller et al., “Maskless Mesoscale Materials Deposition”, Deposition Technology, Sep. 2001, p. 20-22.
Miller, “New Laser-Directed Deposition Technology”, Microelectronic Fabrication, Aug. 2001, p. 16.
Webpage, Object Prototyping the Future, Objet FullCure 700 Series, 1 page.
Webpage, Objet Prototyping the Future, How it Works, 2 pages.
U.S. patent application No. 09/511,986, filed Feb. 24, 2000, entitled “Stereolithographically Fabricated Conductive Elements, Semiconductor Device Components and Assemblies Including Such Conductive Elements, and Methods”, inventor Vernon M. Williams.
U.S. patent application No. 10/201,208, filed Jul. 22, 2002, entitled “Thick Solder Mask for Confining Encapsulant Material Over Selected Locations of a Substrate, Assemblies Including the Solder Mask, and Methods”, inventor Grigg et al.
U.S. patent application No. 10/619,963, filed Jul. 15, 2003, entitled “Sterolithographic Methods for Securing Conductive Elements to Contacts of Semiconductor Device Components”, inventor Vernon M. Williams.
U.S. patent application No. 10/648,163, filed Aug. 26, 2003, entitled “Method for Fabricating an Interposer”, inventor Akram et al.
U.S. patent application No. 10/688,354, filed Oct. 17, 2003, entitled “Thick Solder Mask for Confining Encapsulant Material Over Selected Locations of a Substrate and Assemblies Including the Solder Mask”, inventor Grigg et al.
Huynh Andy
Micro)n Technology, Inc.
Nelms David
TraskBritt
LandOfFree
Protective structures for bond wires does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Protective structures for bond wires, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Protective structures for bond wires will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3507064