Patent
1993-04-23
1997-02-11
Harvey, Jack B.
G06F 1300
Patent
active
056030371
ABSTRACT:
A system for power management within a microprocessor by selectively interrupting clock drivers to a Translation Lookaside Buffer (TLB) unit. The present invention interrupts the clock supply to the TLB unit when the TLB unit is disabled by the microprocessor and during periods of time when it is not anticipated that the TLB unit will be accessed. The present invention monitors a page disable bit to indicate when paging is not required within the microprocessor. Further, the present invention monitors instructions within an instruction queue to determine which may utilize the TLB unit for address translation operations. By interrupting the clock supply, the TLB unit (composed of BiCMOS or CMOS circuits) will not consume power when the unit is not needed. The present invention also includes a mechanism for detecting when the TLB unit is to be used and for powering up the unit. The present invention also includes circuitry for preventing the TLB unit from powering down when the TLB unit is busy. The present invention is particularly useful within portable computer systems (i.e., laptop and pen-based systems) where power conservation is a premium concern.
REFERENCES:
patent: 5167024 (1992-11-01), Smith et al.
patent: 5220672 (1993-06-01), Nakao et al.
patent: 5233696 (1993-08-01), Suzuki
patent: 5237671 (1993-08-01), Freitas et al.
patent: 5255379 (1993-10-01), Melo
patent: 5392437 (1995-02-01), Matter et al.
Harvey Jack B.
Intel Corporation
Travis John
LandOfFree
Clock disable circuit for translation buffer does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Clock disable circuit for translation buffer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Clock disable circuit for translation buffer will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-350661