Wafer scale integration device with dummy chips and relay pads

Details Wafer scale integration device with dummy chips and relay pads Wafer scale integration device with dummy chips and relay pads

1991-05-28

1992-08-11

Hille, Rolf

357 45, H01L 2702

Patent

active

051384191

ABSTRACT:
A wafer scale integration device comprises a plurality of real chips formed in the center portion of a wafer and a plurality of dummy chips formed in the circumference of the wafer. The dummy chips only include relay pads, some of the relay pads are used for relaying bonding wires of power supply lines. Consequently, the power supply lines do not short-circuit at edge portions of the wafer, since a length of the bonding wire at the edge portion of the wafer becomes short due to the relay pad connected to the bonding wire.

REFERENCES:
patent: 4703436 (1987-10-01), Varshney
patent: 5032889 (1991-07-01), Murao et al.
"Wafer-scale integration", Catt, Wireless World, Jul. 1981.
"WASP-A Wafer-scale Systolic Processor" by Hedlund, IEEE International Conference on Computer Design, 1985.

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