Linear voltage subtractor/adder circuit and MOS differential...

Details Linear voltage subtractor/adder circuit and MOS differential... Linear voltage subtractor/adder circuit and MOS differential...

2005-02-01

2005-02-01

Nguyen, Minh (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific input to output function

Combining of plural signals

C327S563000, C330S253000

Reexamination Certificate

active

06850109

ABSTRACT:
A voltage subtractor/adder circuit has a differential pair having first and second MOS transistors. Gate electrodes of the first and second MOS transistors form input terminals for receiving an input differential voltage. Drain electrodes of the first and second MOS transistors form output terminals for outputting a subtraction output signal. Source electrodes of the first and second MOS transistors are commonly coupled to form an output terminal for addition output voltage. The sum of currents flowing through the first and second MOS transistors increases in proportion to the square of the input differential voltage. It is also possible to drive the differential pair by a constant current source. A level shifter may be provided for level-shifting the addition output voltage from the commonly coupled source electrodes.

REFERENCES:
patent: 5381113 (1995-01-01), Kimura
patent: 5594383 (1997-01-01), Tamba
patent: 5602509 (1997-02-01), Kimura
patent: 07-127887 (1995-05-01), None
patent: 2556293 (1996-09-01), None
R. R. Torrance et al., “CMOS Voltage to Current Transducers”,IEEE Transactions on Circuits and Systems, vol. CAS-32, No. 11, Nov. 1985, pp. 1097-1104.
K. Kimura, “MOS Linear and Square-Law Transconductance Amplifiers Consisting of a Source-Coupled Pair with Load Transistors and a Quandritail Cell Using Only N-Channel MOS Unit Transistors”,Technical Report of IEICE, CAS98-41, NLP98-49, Jul. 1998, pp. 17-24.

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