Non-volatile memory control and data loading architecture for mu

Details Non-volatile memory control and data loading architecture for mu Non-volatile memory control and data loading architecture for mu

1995-05-19

1997-04-22

Shah, Alpesh M.

Boots, shoes, and leggings

3642328, 3642329, 3642323, 3642384, 364DIG1, G06F 1576

Patent

active

056236867

ABSTRACT:
An architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.
An input data register on the non-volatile memory die and a related multiplexer allows data from different sources to be loaded into the input data register depending on the mode of operation. Also, the output of the input data register is coupled to plural locations so that the destination of the data can also be switched responsive to the mode of operation. Particularly, the output of the input data register is coupled to an output port, a program data register (through which program data can be loaded into the program memory), and a control register for setting various control bits for performing specific integrity tests which can be performed following fabrication. Accordingly, the input data register is used for programming the memory from an external source, setting control bits from an external device, and sending data from the processor to the R port and on to external devices.

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