Operation method for non-volatile memory

Details Operation method for non-volatile memory Operation method for non-volatile memory

2005-11-08

2005-11-08

Tran, Michael (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185240

Reexamination Certificate

active

06963508

ABSTRACT:
An operation method for non-volatile memory is conducted as follows. First, a non-volatile memory cell capable of storing a first bit and a second bit is provided. The non-volatile memory cell comprises a first region and a second region with a channel therebetween and a gate above the channel but separated therefrom by a charge trapping layer, wherein the first bit and the second bit are positioned close to the first and second regions, respectively. Next, a first programmed voltage for the first bit, a second programmed voltage for the second bit and an erased voltage for the first and second bits are determined, wherein the first programmed voltage is smaller than the second programmed voltage. For reading the first bit, a voltage is applied to the second region, inducing a depletion region around the second region. For reading the second bit, a voltage is applied to the second region, wherein the voltage applied to the second region is smaller than that for reading the first bit.

REFERENCES:
patent: 6011725 (2000-01-01), Eitan
patent: 6873552 (2005-03-01), Ishii et al.
patent: 6888758 (2005-05-01), Hemink et al.

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