Patent
1994-07-25
1997-04-22
Harvey, Jack B.
395726, 395739, 395740, 395742, G06F 1300
Patent
active
056236735
ABSTRACT:
A computer system is provided that includes an interrupt driven system management mode during which system management code is accessed. In one embodiment, a lock-out register is provided to prevent accesses to the system management code while the computer system is operating in its normal mode. In one embodiment, an interrupt control unit is coupled to the ICE interrupt line of the microprocessor core, and controls a memory control unit in accordance with assertions of an external "debug" interrupt signal and an external SMM (system management mode) interrupt signal. If the debug interrupt signal is asserted while the microprocessor core is operating in its normal mode, the interrupt control unit responsively asserts the ICE interrupt signal to the microprocessor core, thereby, causing the microprocessor core to execute ICE code. If, however, the SMM interrupt signal is asserted while the microprocessor core is operating in its normal mode, the interrupt control unit responsively asserts an ICE interrupt signal which causes the microprocessor core to commence executing the SMM code. Both the SMM code and ICE code may be mapped within a region of system memory which is common to the mapping of a video controller.
REFERENCES:
patent: 5175853 (1992-12-01), Kardach et al.
patent: 5339437 (1994-08-01), Yuen
patent: 5363500 (1994-11-01), Takeda
patent: 5392420 (1995-02-01), Balmer et al.
patent: 5437039 (1995-07-01), Yuen
Andrade Victor F.
Gephardt Douglas D.
MacDonald James R.
Advanced Micro Devices , Inc.
Harvey Jack B.
Kivlin B. Noel
Travis John
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