Highly scalable glitch-free frequency divider

Details Highly scalable glitch-free frequency divider Highly scalable glitch-free frequency divider

2005-12-06

2005-12-06

Wambach, Margaret R. (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

C327S115000, C327S117000, C327S142000, C327S146000

Reexamination Certificate

active

06973155

ABSTRACT:
The present invention provides for a divider circuit for reducing anomalous output timing pulses. A latch is coupled to the division selection line. A comparator is coupled to the division selection line. A first synchronizer coupled to the output of the latch. A frequency divider is coupled to the output of the synchronizer. A second synchronizer is coupled to the output of the comparator and the output of the frequency divider. There is feedback between the output of the second synchronizer and the enable input of the latch, the reset of the first synchronizer, the reset of the second synchronized, and the reset of the divide by n divider.

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