Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors
Reexamination Certificate
2005-12-13
2005-12-13
Tung, Kee M. (Department: 2671)
Computer graphics processing and selective visual display system
Computer graphic processing system
Plural graphics processors
C345S426000
Reexamination Certificate
active
06975321
ABSTRACT:
A system and method are provided for generating multiple output packets in a single processing pass of a shader in a hardware graphics pipeline. Initially, graphics data is received, after which it is processed utilizing the shader of the hardware graphics pipeline to generate a plurality of output packets. The plurality of output packets is outputted from the shader of the hardware graphics pipeline in the single processing pass.
REFERENCES:
patent: 6236413 (2001-05-01), Gossett et al.
patent: 6259460 (2001-07-01), Gossett et al.
patent: 6392655 (2002-05-01), Migdal et al.
patent: 6593923 (2003-07-01), Donovan et al.
patent: 6690372 (2004-02-01), Donovan et al.
patent: 6690672 (2004-02-01), Klein et al.
patent: 6760033 (2004-07-01), Chen et al.
patent: 6809739 (2004-10-01), Farinelli et al.
patent: 6819325 (2004-11-01), Boyd et al.
patent: 2003/0020741 (2003-01-01), Boland et al.
patent: 2004/0003370 (2004-01-01), Schenk et al.
E. Chan, R. Ng, P. Sen, K. Proudfoot, and P. Hanrahan. Effient Partitioning Of Fragment Shaders For Multipass Rendering O Programmable Graphics Hardware. In SIGGRAPH/EUROGRAPHICS Workshop On Graphics Hardware (2002), pp. 69-78.
E. Lindholm, M. Kilgard, and H. Moreton. A User-Programmable Vertex Engine. In ACM SIGGRAPH 2001, pp. 140-158.
W. Mark and K. Proudfoot. Compiling to a VLIW Fragement Pipeline. In Proceedings of 2001 SIGGRAPH/Eurographics Workshop on Graphics Hardware, pp. 47-55.
C. Wittenbrink. R-Buffer: A Pointerless A-Buffer Hardware Architecture. In Proceedings of The ACM SIGGRAPH/Eurographics Workshop on Graphics Hardware (2001), pp. 73-80.
M. McCool and W. Heidrich. Texture Shaders. In Proceedings of the ACM SIGGRAPH/Eurographics Workshop on Graphics Hardware (1999), pp. 117-126.
M. Olano and A. Lastra. A Shading Language on Graphics Hardware: The PixelFlow Shading System. In Proceedings of SIGGRAPH 1998, pp. 1-10.
M. Peercy, M Olano, J. Airey, and P. Ungar. Interactive Multi-Pass Programmable Shading. In Proceedings of The 27th Annua Conference on Computer Graphics and Interactive Techniques (Jul. 2000), pp. 425-432.
K. Proudfoot, W. Mark, S. Tzvetkov, and P. Hanrahan. A Real-Time Procedural Shading System for Programmable Graphics Hardware. In ACM SIGGRAPH 2001, pp. 159-170.
http://developer.nvidia.com/object/Filter—Blitting.html, May 10, 2001.
“NVIDIA OpenGL Extension Specifications”, NVIDIA Corporation, Nov. 26, 2001.
William R. Mark et al., “The F-Buffer: A Rasterization-Order FIFO Buffer for Multi-Pass Rendering”, SIGGRAPH/Eurographics Graphics Hardware Workshop 2001.
“NVIDIA OpenGL Extension Specifications”, NVIDIA Coporation, Jun. 10, 2003.
Feldman Zatz Harold Robert
Lindholm John Erik
Molnar Steven E.
NVIDIA Corporation
Tung Kee M.
Zilka-Kotab, PC
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