Point-to-point phase-tolerant communication

Details Point-to-point phase-tolerant communication Point-to-point phase-tolerant communication

1994-08-25

1997-04-22

Auve, Glenn A.

395872, 39520013, 395849, G06F 1300, G06F 1516

Patent

active

056236441

ABSTRACT:
A unidirectional point-to-point communication apparatus for communicating messages between two computing resources irrespective of the phase of the messages, length of a communication path between the two computing resources and internal speed of the two computing resources. The communication apparatus has a high speed communication bus coupling a transmitter and a receiver for transmitting the messages from the transmitter to the receiver. A high speed communication clock is coupled to the bus and the receiver for timing the messages transmitted on the high speed communication bus between transmitter and the receiver. A large data buffer is coupled to the high speed communication bus after the receiver for storing messages transmitted between the transmitter and the receiver. A buffer accessing circuit is coupled to the buffer for referencing write locations to store the messages received from the transmitter over the communication bus, and for referencing read locations for reading the messages out of the buffer by the receiver. Finally, a delay locked loop circuit is coupled to the communication bus, the buffer accessing circuit and the buffer for providing the proper set-up and hold time requirements for the messages transmitted on the communication bus from the transmitter and storing the messages in the buffer.

REFERENCES:
patent: 4771391 (1988-09-01), Blasbalg
patent: 4901277 (1990-02-01), Soloway et al.
patent: 5218677 (1993-06-01), Bono et al.
patent: 5357616 (1994-10-01), Ban
patent: 5377325 (1994-12-01), Chan
patent: 5450548 (1995-09-01), Matsushima
patent: 5491812 (1996-02-01), Pisello et al.

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