Multi-chip package (MCP) with a conductive bar and method...

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor

Reexamination Certificate

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C438S109000, C438S125000

Reexamination Certificate

active

06908785

ABSTRACT:
A multi-chip package (MCP) is provided. The MCP comprises a plurality of stacked semiconductor chips, each including a chip pad and a first insulating layer overlying the chip pad with an opening to expose a portion of the chip pad. Each chip additionally includes a pad redistribution line formed on the first insulating layer and a second insulating layer covering the pad redistribution line. A via hole is formed through the chip, the first insulating layer, a pad redistribution line and the second insulating layer. The MCP further includes a protective layer formed on the bottom of the lowest semiconductor chip. The protective layer includes a conductive pad formed opposite the bottom of the lowest semiconductor chip. A conductive bar extends through the via holes of the stacked semiconductor chips, from the conductive pad, and is electrically connected to the pad redistribution line of the stacked semiconductor chips.

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English language abstract for Japanese Patent No. 06-291250.
English language abstract for Japanese Patent No. 08-264712.
English language abstract for Japanese Patent No. 10-163411.
English language abstract for Japanese Publish Application No 2000-260933.

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