Auto-linking of function logic state with testcase...

Details Auto-linking of function logic state with testcase... Auto-linking of function logic state with testcase...

2005-08-23

2005-08-23

Wachsman, Hal (Department: 2857)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

C702S118000, C702S119000, C716S030000

Reexamination Certificate

active

06934656

ABSTRACT:
A method and system for identifying logic function areas, which make up a virtual machine, that are affected by specific testcases. A Hardware Descriptor Language (HDL) is used to create a software model of the virtual machine. A simulator compiles and analyzes the HDL model, and creates a matrix scoreboard identifying logic function areas in the virtual machine. A complete list of testcases is run on the virtual machine while a monitor correlates each testcase with affected logic function areas to fill in the matrix scoreboard. When a subsequent test failure occurs, either because of a modification to a logic function area, or the execution of a new test, all logic function areas that are affected, either directly or indirectly, are identified.

REFERENCES:
patent: 6212667 (2001-04-01), Geer et al.
patent: 6601229 (2003-07-01), Niederer et al.
patent: 2004/0216077 (2004-10-01), Roesner et al.

Affiliated with

Also associated with

Rating

Auto-linking of function logic state with testcase... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Auto-linking of function logic state with testcase..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Auto-linking of function logic state with testcase... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3490756