Test pattern generation for logic circuits with reduced backtrac

Details Test pattern generation for logic circuits with reduced backtrac Test pattern generation for logic circuits with reduced backtrac

1994-04-05

1997-02-11

Canney, Vincent P.

Excavating

39518306, G06F 1100

Patent

active

056028563

ABSTRACT:
A scheme for generating test patterns for logic circuits which can generate the test patterns effectively and efficiently by making the assignments of the fewer logic values at earlier stages, so as to reduce the number of backtracking operations required. A test pattern for a logic circuit given by primary input logic values for setting a logic value of a specified signal line within the logic circuit at a specified level is generated by: checking whether a fault can be propagated to the specified signal line or not; deriving other signal lines whose logic values are uniquely determinable from the specified level of the specified signal line, only when it is judged that the fault cannot be propagated to the specified signal line; judging whether the primary inputs are contained among the derived other signal lines; and making an assignment of the specified level to the specified signal line, and setting the uniquely determinable logic values for those of the other signal lines which are judged as the primary inputs as the primary input logic values giving the test pattern.

REFERENCES:
patent: 3961250 (1976-06-01), Snethen
patent: 4204633 (1980-05-01), Goel
patent: 5410552 (1995-04-01), Hosokawa
Article entitled, On The Acceleration of Test Generation Algorithms, by Hideo Fujiwara from IEEE Transactions on Computers, vol. C-32 No. 12 dated Dec. 12, 1983; and Article entitled, An Implicit Enumeration Alogorithm to Generate Tests for Combinational Logic Circuits by Prabhakar Goel and dated Mar. 1981 from IEEE Transactions on Computers, vol. C-30, No. 3.

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